Intel and VJ Technologies to Present Pad Site Dress Methods at SMTAI 2010

This study compares manual and semi-automated Printed Circuit Board (PCB) pad site dress methods. Each method is analyzed to understand which method can prevent board damage to the PCB pads such as pad lift, pad cratering and solder mask web damage on various Ball Grid Array (BGA) package types. One socket and two BGA land array patterns were used, as well as two PCB suppliers and three socket suppliers when the study was conducted. The site redress experiments were conducted in three phases.

The rework reflow CTF parameters used for removal and placement of the BGA and socket can weaken the PCB pads during the rework process. The PCB pad site dress method can induce the most significant damage when not implanted properly, due to the inexperience of the operator performing the task and how well they are trained on the method they use.

The results from the three different studies for PCB pad site dress methods on BGA and socket pad arrays will provide insight on which techniques performed best for either of the two component sites from a time zero first pass yield assessment. The findings will be based on e-test for opens and x-ray for solder joint bridging. Failure analysis (FA) via cross sections will highlight any findings such as component solder joint mis-alignment and PCB pad crater. Die and pull was used to identify the same defects as well.