The tool-of-choice for many leading semiconductor suppliers, Talus has already been used for multiple 28- and 20-nanometer (nm) tapeouts. It is particularly effective on designs with a large number of timing modes and sign-off corners. Recently, a key Magma customer was able to implement a challenging 28-nm, 3.5-million-instance SoC top level design with 12 sign-off scenarios in less than 3 days – with full composite current source (CCS) models, multi-mode, multi-corner (MMMC) and crosstalk analysis enabled. Seamless integration of Talus’ implementation and sign-off engines also shortened final sign-off runtime and significantly reduced the number of ECO cycles.
“A key component of Magma’s Silicon One technology solutions, Talus was architected to increase designer productivity, improve quality of results and reduce the development costs of advanced-node designs,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “The rapid rate of adoption by leading semiconductor companies worldwide indicates that Magma is delivering the innovative technology needed to address today’s toughest design challenges.”
Talus 1.2: Faster Turnaround Times, Superior Results
Key enabling technologies in Talus 1.2 include the Talus MX timing and extraction engines based on underlying technology borrowed from Magma's next-generation sign-off timer, Tekton™, and sign-off extractor, QCP™. Used consistently throughout Talus 1.2's RTL-to-GDSII flow, these analysis engines are fast, accurate and have significantly higher capacity. They offer new features such as advanced on-chip variation (AOCV) and MMMC analysis, ensuring tight timing correlation throughout the flow. When combined with Tekton and QCP, Talus 1.2 provides sign-off-accurate analysis during implementation, eliminating timing ECOs and resulting in faster design closure.
For implementation at 28 nm and below, it's not uncommon for designs to require the analysis of many different timing scenarios. Magma defines timing scenarios as the number of process corners multiplied by the number of timing modes. Most solutions can only handle five to eight scenarios during implementation. Talus 1.2 performs concurrent MMMC on a single machine and can manage five times more scenarios than traditional solutions, while improving runtime by 10 times.
For high-performance core design Talus 1.2 features significantly enhanced full-flow hold-corner planning and management to counter high OCV margins at smaller nodes. Combined data and clock optimization ensures robust multi-corner clocks are maintained throughout the flow, simplifying final closure and avoiding ECO congestion.
Talus 1.2's routing technology addresses routing challenges at 28 nm and below, where managing crosstalk in particular becomes more difficult. Fixing crosstalk too late in the flow results, at best, in higher cell area and elevated leakage. In the worst case, it results in a design that will not close. Talus1.2 avoids this by identifying and controlling crosstalk throughout implementation, providing a much more convergent flow with far fewer timing surprises. Unlike other approaches, Talus 1.2 delivers far shorter runtimes and more robust designs, without increasing area and leakage.
For more information, download the white paper Addressing 32/28-nm IC Implementation Challenges with Talus Vortex and Talus Vortex FX from the Magma website at: www.magma-da.com/resources (requires registration).